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[Other] ddr_ctrlv

Description: ddr ram controller vhdl code
Platform: | Size: 55711 | Author: heyong | Hits:

[SourceCode] DDR（双速率）SDRAM控制器参考设计VHDL代码

Description: SDRAM的控制程序很复杂，这个对大家肯定有帮助！
Platform: | Size: 1022145 | Author: zsy5460 | Hits:

[VHDL-FPGA-Verilog] zbt_rd_vhdl_str_v1.0.0

Description: ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules
Platform: | Size: 1688576 | Author: li ji wei | Hits:

[Embeded-SCM Develop] ddr_ddr2_sdram

Description: 基于NIOS II的ddr2控制器,配有详细的文档,经验证后可使用.-NIOS II based on the DDR2 controller, equipped with detailed documentation, the experience can be used after certification.
Platform: | Size: 3486720 | Author: Jackie | Hits:

[VHDL-FPGA-Verilog] LVDS_DDR_List_FPGA2

Description: FPGA芯片与ADI公司的AD9779之间的通信，总共有四个通道，68对LVDS,采样时钟是122.88MHz-FPGA chips ADI' s AD9779 and communication between, a total of four channels, 68 pairs of LVDS, the sampling clock is 122.88MHz
Platform: | Size: 808960 | Author: linpingping | Hits:

[VHDL-FPGA-Verilog] xapp860

Description: 16通道DDR的LVDS接口（VHDL,Verilog and doc）-16-Channel, DDR LVDS Interface with Real-Time Window Monitoring
Platform: | Size: 650240 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: 用vdhl编写的DDR sdram控制器，采用模块化编写，条理清楚，注解详细，附有存储器的说明。-the ddr sdram controller base vhdl
Platform: | Size: 476160 | Author: tangjieling | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the vhdl testbench, modelsim project file, and library \source Contains the vhdl source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 897024 | Author: chen | Hits:

[VHDL-FPGA-Verilog] ddr_sdr

Description: ddr ram控制器，使用vhdl语言实现-ddr ram controller,designed by vhdl
Platform: | Size: 115712 | Author: 东 | Hits:

[VHDL-FPGA-Verilog] DDR_FLASH_VHDL_Verilog

Description: FPGA DDR 外部RAM 读写的verilog代码，以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
Platform: | Size: 17408 | Author: rickdecent | Hits:

[Software Engineering] DDRSDRAM

Description: 基于VHDL的DDR SDRAM控制器的设计，实现数据的读写功能，迸发长度分为2，4，8-Based on the VHDL DDR SDRAM controller design, implementation of data read and write capabilities, burst into the length of 2, 4, 8
Platform: | Size: 823296 | Author: zhangjiefei | Hits:

[VHDL-FPGA-Verilog] ddr_sdr_latest.tar

Description: DDR 控制器 control verilog/vhdl 源代码 -ddr control source of verilog /vhdl
Platform: | Size: 80896 | Author: 陈成 | Hits:

[Other] DDR3_DD12

Description: DRR3 peripheral test for Microblaze processor on Spartan-6
Platform: | Size: 13840384 | Author: kilometrix | Hits:

[VHDL-FPGA-Verilog] VmodCAM_Ref_HD Demo_13

Description: This project has dependencies in the 'digilent' VHDL library. For your convenience a local copy of these dependencies are included in the remote_sources directory. The VmodCAM_Ref_HD demo project was built around an Atlys+VmodCAM setup. The project configures the two cameras on the VmodCAM for maximum resolution and frame rate, RGB output and video snapshot mode. The DDR memory on-board the Atlys is used as a frame buffer. The two video feeds from both cameras are bufferd in the DDR, while the FPGA drives the HDMI out port with either of the cameras. Switch 7 selects the camera which gets displayed. The resolution of the cameras (1600x1200) gets cropped to fit the display resolution of 1600x900. Project built in ISE 13.2, tested in ISE 13.1.
Platform: | Size: 13762560 | Author: domnish | Hits:
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